There are various semiconductor packages for semiconductor chips such as TSOP, MSOP and QSOP which are implemented in memory devices or memory cards in consumer electronics. The most popular packages for memory devices are leadframe-based LOC (Lead-On-Chip) packages and COL (Chip-On-Lead) packages where LOC packages including semiconductor chips disposed under the leads are designed for chips with central pads and COL packages including semiconductor chips disposed on top of the leads are designed for chips with peripheral pads. When packaging multiple chips within in a COL package, small chips usually cause uneven encapsulant distribution and affect mold flow balance.
As shown in FIG. 1 and FIG. 2, a conventional COL type semiconductor package 100 comprises a plurality of leadframe's leads 110, a wiring substrate 120, a first chip 130, a second chip 140, and an encapsulant 150. The leads 110 includes a plurality of first side leads 112 and a plurality of second side leads 113 where the first side leads 112 are longer than the second side leads 113 to support the chips 130, 140 and the wiring substrate 120. The first chip 130 is a controller chip with a smaller dimension and the second chip 140 is a flash memory with a larger dimension. The wiring substrate 120 is to integrate electrical signals between the chips 130, 140 within the package 100. During packaging of 3D stacking, the component with larger dimension is stacked first followed by component with a smaller dimension where the second chip 140 is disposed on the second side leads 113 and the wiring substrate 120 is disposed on the second chip 140 and the first chip 130 is disposed on the wiring substrate 120. The wiring substrate 120 is electrically connected to the leads 110 by a plurality of first bonding wires 161, the second chip 140 is electrically connected to the wiring substrate 120 by a plurality of second bonding wires 162 and the first chip 130 is electrically connected to the wiring substrate 120 by a plurality of third bonding wires 163, so that the first chip 130, the second chip 140, the wiring substrate 120 and the leads 110 are all electrically connected together. The encapsulant 150 encapsulates a plurality of internal parts 111A of the leads 110, the wiring substrate 120, the first chip 130 and the second chip 140 with a plurality of external parts of the leads 110 extend and bend downward from two corresponding sides of the encapsulant 150 for external electrical connections.
In the conventional COL type semiconductor package, the first chip 130 with a smallest dimension is stacked on the most top of the stacked structure. Since the first chip 130 is smaller and extruded from the leads 110 during the molding of the encapsulant 150, so that the mold cavity above the leads becomes larger with uneven encapsulant distribution leading to unbalanced encapsulant 150 above and below the leads 110 and unbalanced encapsulant 150 between center and peripheries. When temperature changes, the encapsulant 150 expands due to high temperature or shrink due to low temperature leading to warpage of the semiconductor package 100. Furthermore, unbalanced mold flow above and below leads 110 is an issue as well.